Researchers from TSMC and National Yang Ming Chiao Tung University (NYCU) have pulled off a major breakthrough in two-dimensional semiconductor tech. By zooming in on the atomic boundary where materials meet, the team built an ultrathin interface layer just 0.42 nanometers thick inside experimental molybdenum disulfide (MoS2) field-effect transistors. The work, recently published in Nature Electronics, tackles one of the biggest bottlenecks in post-silicon chip design: keeping electron mobility high while shrinking gate insulator thickness to maintain precise electrostatic control.
Instead of hunting for entirely new semiconductor materials, the engineers re-engineered the crucial boundary separating the single-atom-thick MoS2 channel from its gate dielectric. Using an ultra-high vacuum process, they laid down an epitaxial layer of aluminum directly on MoS2 produced via chemical vapor deposition. By carefully controlling how that aluminum oxidized, they created a smooth 0.42-nanometer aluminum oxide buffer beneath a high-k hafnium oxide gate dielectric. This sub-nanometer layer does double duty—it provides an even base for uniform dielectric growth while protecting charge carriers from the interface scattering that usually wrecks performance in ultra-scaled transistors.
The resulting top-gate transistors achieved an equivalent oxide thickness of about one nanometer alongside a transconductance of 0.45 mS per micrometer, proving that sharp dielectric scaling and top-tier carrier performance can go hand-in-hand in 2D electronics. While 0.42 nanometers describes an experimental component dimension rather than a commercial chip node size, TSMC's direct involvement shows how seriously major chipmakers are taking 2D channel materials as traditional silicon nanosheets hit physical brick walls past the sub-2nm mark.